// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:09 UTC 2022
//////////////////////////////////////////////////////////////////////////////
//
//  pcs_raw_cmn.v
//
//  Raw PCS common control module
//
//  Original Author: Ameer Youssef
//  Current Owner:   Dom Spagnuolo
//
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
//////////////////////////////////////////////////////////////////////////////
//
//    Perforce Information
//    $Author: yilin $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_cmn.v $
//    $DateTime: 2016/06/28 15:04:07 $
//    $Revision: #60 $
//
//////////////////////////////////////////////////////////////////////////////

`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"
`include "dwc_e12mp_phy_x4_ns_cr_macros.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_cmn (
// Clocks and resets
input  wire                       cr_ext_clk,
input  wire                       cr_ext_clk_rst,
input  wire                       cr_clk,
input  wire                       cr_rst,
output wire                       phy_func_reset,

//----------------------------------------------
// PHY inputs
input  wire                       mplla_force_en,
input  wire                       mpllb_force_en,

input  wire [`DWC_E12MP_X4NS_MPLL_BW_RANGE] mplla_bandwidth,
input  wire [2:0]                 mplla_ssc_range,
input  wire [8:0]                 mplla_fracn_ctrl,
input  wire [2:0]                 mplla_ssc_clk_sel,
input  wire                       mplla_ssc_en,
input  wire [`DWC_E12MP_X4NS_MPLL_BW_RANGE] mpllb_bandwidth,
input  wire [2:0]                 mpllb_ssc_range,
input  wire [8:0]                 mpllb_fracn_ctrl,
input  wire [2:0]                 mpllb_ssc_clk_sel,
input  wire                       mpllb_ssc_en,

input  wire                       rtune_req,
//----------------------------------------------

// Internal from Raw PCS lanes (pcs_raw_lane)
input  wire                       lane_mplla_en_in,
input  wire                       lane_mpllb_en_in,
input  wire                       lane_rtune_req_in,

// Internal to Raw PCS lanes (pcs_raw_lane) (Mantis 5662)
output wire                       cmn_mplla_en_out,
output wire                       cmn_mpllb_en_out,

// Mantis 6728 - Generate fw_rdy signal to lanes
output wire                       fw_rdy,

//----------------------------------------------
// Outputs to PMA
output reg                        mplla_en,
output reg                        mpllb_en,

output wire [`DWC_E12MP_X4NS_MPLL_BW_RANGE] pma_mplla_bandwidth,
output wire [2:0]                 pma_mplla_ssc_range,
output wire [8:0]                 pma_mplla_fracn_ctrl,
output wire [2:0]                 pma_mplla_ssc_clk_sel,
output wire                       pma_mplla_ssc_en,
output wire [`DWC_E12MP_X4NS_MPLL_BW_RANGE] pma_mpllb_bandwidth,
output wire [2:0]                 pma_mpllb_ssc_range,
output wire [8:0]                 pma_mpllb_fracn_ctrl,
output wire [2:0]                 pma_mpllb_ssc_clk_sel,
output wire                       pma_mpllb_ssc_en,

output reg                        pma_rtune_req,
//----------------------------------------------

// CREG parallel interface
input  wire                       cr_para_sel_i, // from aon block
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr_para_addr,
input  wire                       cr_para_wr_en,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_para_wr_data,
input  wire                       cr_para_rd_en,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_para_rd_data,
output wire                       cr_para_ack,

// -----------------------------------------------
// Internal to/from pcs_raw_aon_cmn
// -----------------------------------------------
output wire [31:0]                cr_cmn_aon_sel,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_cmn_aon_rd_data,

// JTAG interface
input  wire                       jtag_trst_n,
//input  wire                       jtag_tck, // goes instead to pcs_raw_aon_cmn
input  wire                       jtag_clk,   // from pcs_raw_aon_cmn
input  wire                       jtag_clk_n, // from pcs_raw_aon_cmn
input  wire                       jtag_tms,
input  wire                       jtag_tdi,
output wire                       jtag_tdo,
output wire                       jtag_tdo_en,

// Scan Signals
input  wire                       scan_mode,
input  wire                       scan_shift,
input  wire                       scan_shift_cg,
input  wire                       scan_set_rst,
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
input  wire                       scan_cr_clk,
`endif

// CREG parallel interface (for Raw PCS lane and PMA registers
// (i.e. all registers except Raw PCS common)
output wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr_addr,
output wire                       cr_wr_en,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_wr_data,
output wire                       cr_rd_en,

// CREG read data from PMA
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_pma_rd_data,

// CREG read data from Raw PCS lanes
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr0_rd_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr1_rd_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr2_rd_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr3_rd_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr4_rd_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr5_rd_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr6_rd_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr7_rd_data,

//----------------------------------------------
// External SRAM interface
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
input  wire                       sram_bypass,
input  wire                       sram_init_done_in,  // from AON domain
output wire                       sram_init_done_out, // to AON domain
input  wire                       sram_ext_ld_done,


output wire                       sram_clk,
output wire                       sram_rd_en,
output wire                       sram_wr_en,
output wire [`DWC_E12MP_X4NS_SRAM_ADDR_RANGE] sram_addr,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] sram_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] sram_rd_data,
`endif

// --------------------------------------------------
// CREG interface with Memory-Arbiter
// --------------------------------------------------
output wire                       cr0_mem_ack,
output wire                       cr1_mem_ack,
output wire                       cr2_mem_ack,
output wire                       cr3_mem_ack,
output wire                       cr4_mem_ack,
output wire                       cr5_mem_ack,
output wire                       cr6_mem_ack,
output wire                       cr7_mem_ack,

output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr0_mem_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr1_mem_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr2_mem_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr3_mem_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr4_mem_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr5_mem_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr6_mem_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr7_mem_rd_data,

input  wire                       cr0_mem_req,
input  wire                       cr1_mem_req,
input  wire                       cr2_mem_req,
input  wire                       cr3_mem_req,
input  wire                       cr4_mem_req,
input  wire                       cr5_mem_req,
input  wire                       cr6_mem_req,
input  wire                       cr7_mem_req,

input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr0_mem_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr1_mem_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr2_mem_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr3_mem_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr4_mem_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr5_mem_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr6_mem_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr7_mem_addr,

input  wire                       cr0_mem_wr_en,
input  wire                       cr1_mem_wr_en,
input  wire                       cr2_mem_wr_en,
input  wire                       cr3_mem_wr_en,
input  wire                       cr4_mem_wr_en,
input  wire                       cr5_mem_wr_en,
input  wire                       cr6_mem_wr_en,
input  wire                       cr7_mem_wr_en,

input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr0_mem_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr1_mem_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr2_mem_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr3_mem_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr4_mem_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr5_mem_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr6_mem_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr7_mem_wr_data,

input  wire                       cr0_mem_rd_en,
input  wire                       cr1_mem_rd_en,
input  wire                       cr2_mem_rd_en,
input  wire                       cr3_mem_rd_en,
input  wire                       cr4_mem_rd_en,
input  wire                       cr5_mem_rd_en,
input  wire                       cr6_mem_rd_en,
input  wire                       cr7_mem_rd_en,

// --------------------------------------------------
// CREG interface with Register-Arbiter
// --------------------------------------------------
output wire                       cr0_reg_ack,
output wire                       cr1_reg_ack,
output wire                       cr2_reg_ack,
output wire                       cr3_reg_ack,
output wire                       cr4_reg_ack,
output wire                       cr5_reg_ack,
output wire                       cr6_reg_ack,
output wire                       cr7_reg_ack,

output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr0_reg_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr1_reg_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr2_reg_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr3_reg_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr4_reg_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr5_reg_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr6_reg_rd_data,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr7_reg_rd_data,

input  wire                       cr0_reg_req,
input  wire                       cr1_reg_req,
input  wire                       cr2_reg_req,
input  wire                       cr3_reg_req,
input  wire                       cr4_reg_req,
input  wire                       cr5_reg_req,
input  wire                       cr6_reg_req,
input  wire                       cr7_reg_req,

input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr0_reg_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr1_reg_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr2_reg_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr3_reg_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr4_reg_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr5_reg_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr6_reg_addr,
input  wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] cr7_reg_addr,

input  wire                       cr0_reg_wr_en,
input  wire                       cr1_reg_wr_en,
input  wire                       cr2_reg_wr_en,
input  wire                       cr3_reg_wr_en,
input  wire                       cr4_reg_wr_en,
input  wire                       cr5_reg_wr_en,
input  wire                       cr6_reg_wr_en,
input  wire                       cr7_reg_wr_en,

input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr0_reg_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr1_reg_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr2_reg_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr3_reg_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr4_reg_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr5_reg_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr6_reg_wr_data,
input  wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr7_reg_wr_data,

input  wire                       cr0_reg_rd_en,
input  wire                       cr1_reg_rd_en,
input  wire                       cr2_reg_rd_en,
input  wire                       cr3_reg_rd_en,
input  wire                       cr4_reg_rd_en,
input  wire                       cr5_reg_rd_en,
input  wire                       cr6_reg_rd_en,
input  wire                       cr7_reg_rd_en
);

// ------------------------
// Nets declarations
// ------------------------

// Internal CREG Interface

wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_arbt_reg_addr;
wire                              cr_arbt_reg_wr_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_arbt_reg_wr_data;
wire                              cr_arbt_reg_rd_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_arbt_reg_rd_data;

wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_addr_int;
wire                              cr_wr_en_int;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_wr_data_int;
wire                              cr_rd_en_int;

wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_arbt_mem_addr;
wire                              cr_arbt_mem_wr_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_arbt_mem_wr_data;
wire                              cr_arbt_mem_rd_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_arbt_mem_rd_data;

wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_mem_addr;
wire                              cr_mem_wr_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_mem_wr_data;
wire                              cr_mem_rd_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_mem_rd_data;

wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_addr;
wire                              cr_ext_wr_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_wr_data;
wire                              cr_ext_rd_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_rd_data;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_rd_data_arbt;
wire                              cr_ext_ack;
wire                              cr_ext_arbt_ack;

wire                              cr_ext_mem_req;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_mem_addr;
wire                              cr_ext_mem_wr_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_mem_wr_data;
wire                              cr_ext_mem_rd_en;
wire                              cr_ext_mem_ack;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_mem_rd_data;

wire                              cr_ext_reg_req;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_reg_addr;
wire                              cr_ext_reg_wr_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_reg_wr_data;
wire                              cr_ext_reg_rd_en;
wire                              cr_ext_reg_ack;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_reg_rd_data;

wire                              cr8_reg_req;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr8_reg_addr;
wire                              cr8_reg_wr_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr8_reg_wr_data;
wire                              cr8_reg_rd_en;
wire                              cr8_reg_ack;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr8_reg_rd_data;

wire                              cr8_mem_req;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr8_mem_addr;
wire                              cr8_mem_wr_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr8_mem_wr_data;
wire                              cr8_mem_rd_en;
wire                              cr8_mem_ack;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr8_mem_rd_data;

wire                              cr_raw_cmn_reg_req;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_raw_cmn_reg_addr;
wire                              cr_raw_cmn_reg_wr_en;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_raw_cmn_reg_wr_data;
wire                              cr_raw_cmn_reg_rd_en;
wire                              cr_raw_cmn_reg_ack;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_raw_cmn_reg_rd_data;

wire [31:0]                       cr_cmn0_b0_sel;
wire [31:0]                       cr_cmn0_b1_sel;
wire [31:0]                       cr_cmn0_b2_sel;
wire [31:0]                       cr_cmn0_b3_sel;
wire [31:0]                       cr_cmn0_b4_sel;
wire [31:0]                       cr_cmn0_b5_sel;
wire [31:0]                       cr_cmn0_b6_sel;
wire [31:0]                       cr_cmn0_b7_sel;

wire [31:0]                       cr_cmn1_b0_sel;
wire [31:0]                       cr_cmn1_b1_sel;
wire [31:0]                       cr_cmn1_b2_sel;
wire [31:0]                       cr_cmn1_b3_sel;
wire [31:0]                       cr_cmn1_b4_sel;
wire [31:0]                       cr_cmn1_b5_sel;
wire [31:0]                       cr_cmn1_b6_sel;
wire [31:0]                       cr_cmn1_b7_sel;

wire [31:0]                       cr_cmn2_b0_sel;
wire [31:0]                       cr_cmn2_b1_sel;
wire [31:0]                       cr_cmn2_b2_sel;
wire [31:0]                       cr_cmn2_b3_sel;
wire [31:0]                       cr_cmn2_b4_sel;
wire [31:0]                       cr_cmn2_b5_sel;
wire [31:0]                       cr_cmn2_b6_sel;
wire [31:0]                       cr_cmn2_b7_sel;

wire [31:0]                       cr_cmn3_b0_sel;
wire [31:0]                       cr_cmn3_b1_sel;
wire [31:0]                       cr_cmn3_b2_sel;
wire [31:0]                       cr_cmn3_b3_sel;
wire [31:0]                       cr_cmn3_b4_sel;
wire [31:0]                       cr_cmn3_b5_sel;
wire [31:0]                       cr_cmn3_b6_sel;
wire [31:0]                       cr_cmn3_b7_sel;

wire [31:0]                       cr_cmn4_b0_sel;
wire [31:0]                       cr_cmn4_b1_sel;
wire [31:0]                       cr_cmn4_b2_sel;
wire [31:0]                       cr_cmn4_b3_sel;
wire [31:0]                       cr_cmn4_b4_sel;
wire [31:0]                       cr_cmn4_b5_sel;
wire [31:0]                       cr_cmn4_b6_sel;
wire [31:0]                       cr_cmn4_b7_sel;

wire [31:0]                       cr_cmn5_b0_sel;
wire [31:0]                       cr_cmn5_b1_sel;
wire [31:0]                       cr_cmn5_b2_sel;
wire [31:0]                       cr_cmn5_b3_sel;
wire [31:0]                       cr_cmn5_b4_sel;
wire [31:0]                       cr_cmn5_b5_sel;
wire [31:0]                       cr_cmn5_b6_sel;
wire [31:0]                       cr_cmn5_b7_sel;

wire [31:0]                       cr_cmn6_b0_sel;
wire [31:0]                       cr_cmn6_b1_sel;
wire [31:0]                       cr_cmn6_b2_sel;
wire [31:0]                       cr_cmn6_b3_sel;
wire [31:0]                       cr_cmn6_b4_sel;
wire [31:0]                       cr_cmn6_b5_sel;
wire [31:0]                       cr_cmn6_b6_sel;
wire [31:0]                       cr_cmn6_b7_sel;

wire [31:0]                       cr_cmn7_b0_sel;
wire [31:0]                       cr_cmn7_b1_sel;
wire [31:0]                       cr_cmn7_b2_sel;
wire [31:0]                       cr_cmn7_b3_sel;
wire [31:0]                       cr_cmn7_b4_sel;
wire [31:0]                       cr_cmn7_b5_sel;
wire [31:0]                       cr_cmn7_b6_sel;
wire [31:0]                       cr_cmn7_b7_sel;

wire [31:0]                       cr_cmn8_b0_sel;
wire [31:0]                       cr_cmn8_b1_sel;
wire [31:0]                       cr_cmn8_b2_sel;
wire [31:0]                       cr_cmn8_b3_sel;
wire [31:0]                       cr_cmn8_b4_sel;
wire [31:0]                       cr_cmn8_b5_sel;
wire [31:0]                       cr_cmn8_b6_sel;
wire [31:0]                       cr_cmn8_b7_sel;

wire [31:0]                       cr_cmn9_b0_sel;
wire [31:0]                       cr_cmn9_b1_sel;
wire [31:0]                       cr_cmn9_b2_sel;
wire [31:0]                       cr_cmn9_b3_sel;
wire [31:0]                       cr_cmn9_b4_sel;
wire [31:0]                       cr_cmn9_b5_sel;
wire [31:0]                       cr_cmn9_b6_sel;
wire [31:0]                       cr_cmn9_b7_sel;

wire [31:0]                       cr_cmn10_b0_sel;
wire [31:0]                       cr_cmn10_b1_sel;
wire [31:0]                       cr_cmn10_b2_sel;
wire [31:0]                       cr_cmn10_b3_sel;
wire [31:0]                       cr_cmn10_b4_sel;
wire [31:0]                       cr_cmn10_b5_sel;
wire [31:0]                       cr_cmn10_b6_sel;
wire [31:0]                       cr_cmn10_b7_sel;

wire [31:0]                       cr_cmn11_b0_sel;
wire [31:0]                       cr_cmn11_b1_sel;
wire [31:0]                       cr_cmn11_b2_sel;
wire [31:0]                       cr_cmn11_b3_sel;
wire [31:0]                       cr_cmn11_b4_sel;
wire [31:0]                       cr_cmn11_b5_sel;
wire [31:0]                       cr_cmn11_b6_sel;
wire [31:0]                       cr_cmn11_b7_sel;

wire [31:0]                       cr_cmn12_b0_sel;
wire [31:0]                       cr_cmn12_b1_sel;
wire [31:0]                       cr_cmn12_b2_sel;
wire [31:0]                       cr_cmn12_b3_sel;
wire [31:0]                       cr_cmn12_b4_sel;
wire [31:0]                       cr_cmn12_b5_sel;
wire [31:0]                       cr_cmn12_b6_sel;
wire [31:0]                       cr_cmn12_b7_sel;

wire [31:0]                       cr_cmn13_b0_sel;
wire [31:0]                       cr_cmn13_b1_sel;
wire [31:0]                       cr_cmn13_b2_sel;
wire [31:0]                       cr_cmn13_b3_sel;
wire [31:0]                       cr_cmn13_b4_sel;
wire [31:0]                       cr_cmn13_b5_sel;
wire [31:0]                       cr_cmn13_b6_sel;
wire [31:0]                       cr_cmn13_b7_sel;

wire [31:0]                       cr_cmn14_b0_sel;
wire [31:0]                       cr_cmn14_b1_sel;
wire [31:0]                       cr_cmn14_b2_sel;
wire [31:0]                       cr_cmn14_b3_sel;
wire [31:0]                       cr_cmn14_b4_sel;
wire [31:0]                       cr_cmn14_b5_sel;
wire [31:0]                       cr_cmn14_b6_sel;
wire [31:0]                       cr_cmn14_b7_sel;

wire [31:0]                       cr_cmn15_b0_sel;
wire [31:0]                       cr_cmn15_b1_sel;
wire [31:0]                       cr_cmn15_b2_sel;
wire [31:0]                       cr_cmn15_b3_sel;
wire [31:0]                       cr_cmn15_b4_sel;
wire [31:0]                       cr_cmn15_b5_sel;
wire [31:0]                       cr_cmn15_b6_sel;
wire [31:0]                       cr_cmn15_b7_sel;

wire [7:0]                        cr_cmn_sel;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_cmn_rd_data;

wire                              mplla_force_en_sync;
wire                              mpllb_force_en_sync;
wire                              rtune_req_sync;

// Mantis 6775 - CREG to control lane_fsm CREG read/write extension
wire                              lane_fsm_op_xtnd_r;

// JTAG REG XFACE                 
wire                              jtag_rst;
//wire                              jtag_clk;
//wire                              jtag_clk_n;
wire                              jtag_ser_in;
wire                              jtag_capture;
wire                              jtag_shift;
wire                              jtag_update;
wire                              jtag_crsel_sel;
wire                              jtag_crsel_tdo;

wire [11:0]                       prgm_size;

`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
//----------------------------------------------
// External SRAM interface
// Bootloader <-> ROM wires
wire                              cr_mem_rd_en_bl;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_mem_addr_bl;

// Bootloader <-> SRAM wires
wire                              sram_wr_en_bl;
wire [`DWC_E12MP_X4NS_SRAM_ADDR_RANGE]      sram_addr_bl;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        sram_wr_data_bl;

wire                              sram_ext_sel;
wire                              sram_int_sel;
wire                              sram_sel;
wire                              sram_sel_int;
reg  [`DWC_E12MP_X4NS_CR_DATA_RANGE]        sram_rd_data_d;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        sram_rd_data_gated;
reg                               sram_rd_data_vld;
reg  [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_arbt_mem_addr_d;

reg                               cr_ext_rd_en_d;
reg                               cr_ext_rd_en_d2;
reg                               cr_ext_wr_en_d;
reg  [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_addr_d;
reg  [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_wr_data_d;
wire                              cr_ext_byp_sram_ack;
wire                              cr_ext_byp_reg_ack;
reg                               cr_ext_byp_ack;

// Intermediate muxing signals used for SRAM interface
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_arbt_mem_rd_data_or;
wire                              cr_mem_rd_en_int;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_mem_addr_int;
wire                              cr_mem_wr_en_int;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_mem_wr_data_int;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_mem_rd_data_int;

wire                              sram_rd_en_ext_ld;
wire                              sram_wr_en_ext_ld;
wire [`DWC_E12MP_X4NS_SRAM_ADDR_RANGE]      sram_addr_ext_ld;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        sram_wr_data_ext_ld;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_rd_data_ext_ld;

wire                              sram_rd_en_int1;
wire                              sram_wr_en_int1;
wire [`DWC_E12MP_X4NS_SRAM_ADDR_RANGE]      sram_addr_int1;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        sram_wr_data_int1;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_rd_data_int1;

wire                              sram_rd_en_arbt;
wire                              sram_wr_en_arbt;
wire [`DWC_E12MP_X4NS_SRAM_ADDR_RANGE]      sram_addr_arbt;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        sram_wr_data_arbt;

wire                              sram_rd_en_int2;
wire                              sram_wr_en_int2;
wire [`DWC_E12MP_X4NS_SRAM_ADDR_RANGE]      sram_addr_int2;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        sram_wr_data_int2;
wire [`DWC_E12MP_X4NS_CR_DATA_RANGE]        cr_ext_rd_data_int2;

`endif

// JTAG FSM and interface to any external JTAG registers
// Disable scan in powerdown and burnin modes since they supercede scan_mode.
// Note this is done with the pre-scan loopback versions of these controls
//
dwc_e12mp_phy_x4_ns_jtag_ctl jtag_ctl (
  // TAP interface
  .jtag_trst_n           (jtag_trst_n),
  //.jtag_tck              (jtag_tck),
  .jtag_tms              (jtag_tms),
  .jtag_tdi              (jtag_tdi),
  .jtag_tdo              (jtag_tdo),
  .jtag_tdo_en           (jtag_tdo_en),

  .scan_mode             (scan_mode),
  .scan_set_rst          (scan_set_rst),

  // Generic JTAG register control signals
  .jtag_rst              (jtag_rst),
  .jtag_clk              (jtag_clk),
  .jtag_clk_n            (jtag_clk_n),
  .jtag_ser_in           (jtag_ser_in),
  .jtag_capture          (jtag_capture),
  .jtag_shift            (jtag_shift),
  .jtag_update           (jtag_update),

  // Individual JTAG registers
  .jtag_crsel_sel        (jtag_crsel_sel),
  .jtag_crsel_tdo        (jtag_crsel_tdo)
);

// -----------------------------------------------
// Control register FSM
// -----------------------------------------------
dwc_e12mp_phy_x4_ns_pcs_raw_creg_ctl creg_ctl (
  .cr_para_sel_i         (cr_para_sel_i),

  // CR Parallel Interface
  .cr_para_addr          (cr_para_addr),
  .cr_para_wr_en         (cr_para_wr_en),
  .cr_para_wr_data       (cr_para_wr_data),
  .cr_para_rd_en         (cr_para_rd_en),
  .cr_para_rd_data       (cr_para_rd_data),
  .cr_para_ack           (cr_para_ack),

  // JTAG interface to Control registers
  .jtag_rst              (jtag_rst),
  .jtag_clk              (jtag_clk),
  .jtag_clk_n            (jtag_clk_n),
  .jtag_capture          (jtag_capture),
  .jtag_shift            (jtag_shift),
  .jtag_update           (jtag_update),
  .jtag_ser_in           (jtag_ser_in),
  .jtag_crsel_sel        (jtag_crsel_sel),
  .jtag_crsel_tdo        (jtag_crsel_tdo),
  
  // External CR control bus
  .cr_addr               (cr_ext_addr),
  .cr_wr_en              (cr_ext_wr_en),
  .cr_wr_data            (cr_ext_wr_data),
  .cr_rd_en              (cr_ext_rd_en),
  .cr_rd_data            (cr_ext_rd_data),
  .cr_ack                (cr_ext_ack)
);

// -----------------------------------------------------------------
// Control interface between external CREG and Arbiters (Mem & Reg)
// -----------------------------------------------------------------
dwc_e12mp_phy_x4_ns_pcs_raw_ext_arbt_ctl ext_arbt_ctl (
  // CR external clock
  .cr_ext_clk            (cr_ext_clk),
  .cr_ext_clk_rst        (cr_ext_clk_rst),

  // Clock and reset
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),

  // External CR control bus
  .cr_ext_addr           (cr_ext_addr),
  .cr_ext_wr_data        (cr_ext_wr_data),
  // Mantis 7115 - Gate the external arbiter during sram_init and sram_ext_ld phases
  // Use the incoming version of the signal from the AON domain since it is what
  // is actually output.
  `ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
  .cr_ext_wr_en          (cr_ext_wr_en & (sram_bypass | (sram_init_done_in & sram_ext_ld_done))),
  .cr_ext_rd_en          (cr_ext_rd_en & (sram_bypass | (sram_init_done_in & sram_ext_ld_done))),
  `else
  .cr_ext_wr_en          (cr_ext_wr_en),
  .cr_ext_rd_en          (cr_ext_rd_en),
  `endif
  .cr_ext_rd_data        (cr_ext_rd_data_arbt),
  .cr_ext_ack            (cr_ext_arbt_ack),
  
  // Scan
  .scan_mode             (scan_mode),
  .scan_set_rst          (scan_set_rst),
  
  // CR control bus with the Memory arbiter
  .cr_mem_req            (cr_ext_mem_req),
  .cr_mem_addr           (cr_ext_mem_addr),
  .cr_mem_wr_data        (cr_ext_mem_wr_data),
  .cr_mem_wr_en          (cr_ext_mem_wr_en),
  .cr_mem_rd_en          (cr_ext_mem_rd_en),
  .cr_mem_ack            (cr_ext_mem_ack),
  .cr_mem_rd_data        (cr_ext_mem_rd_data),
  
  // CR control bus with the Register arbiter
  .cr_reg_req            (cr_ext_reg_req),
  .cr_reg_addr           (cr_ext_reg_addr),
  .cr_reg_wr_data        (cr_ext_reg_wr_data),
  .cr_reg_wr_en          (cr_ext_reg_wr_en),
  .cr_reg_rd_en          (cr_ext_reg_rd_en),
  .cr_reg_ack            (cr_ext_reg_ack),
  .cr_reg_rd_data        (cr_ext_reg_rd_data)
);

// -----------------------------------------------
// Build input buses to memory arbiter
// -----------------------------------------------
assign cr8_mem_req        = cr_ext_mem_req;
assign cr8_mem_addr       = cr_ext_mem_addr;
assign cr8_mem_wr_en      = cr_ext_mem_wr_en;
assign cr8_mem_wr_data    = cr_ext_mem_wr_data;
assign cr8_mem_rd_en      = cr_ext_mem_rd_en;
assign cr_ext_mem_ack     = cr8_mem_ack;
assign cr_ext_mem_rd_data = cr8_mem_rd_data;

wire [15:0]  crN_mem_req     = {7'd0,   cr8_mem_req    ,cr7_mem_req    ,cr6_mem_req    ,cr5_mem_req    ,cr4_mem_req    ,cr3_mem_req    ,cr2_mem_req    ,cr1_mem_req    ,cr0_mem_req    };
wire [255:0] crN_mem_addr    = {112'd0, cr8_mem_addr   ,cr7_mem_addr   ,cr6_mem_addr   ,cr5_mem_addr   ,cr4_mem_addr   ,cr3_mem_addr   ,cr2_mem_addr   ,cr1_mem_addr   ,cr0_mem_addr   };
wire [255:0] crN_mem_wr_data = {112'd0, cr8_mem_wr_data,cr7_mem_wr_data,cr6_mem_wr_data,cr5_mem_wr_data,cr4_mem_wr_data,cr3_mem_wr_data,cr2_mem_wr_data,cr1_mem_wr_data,cr0_mem_wr_data};
wire [15:0]  crN_mem_wr_en   = {7'd0,   cr8_mem_wr_en  ,cr7_mem_wr_en  ,cr6_mem_wr_en  ,cr5_mem_wr_en  ,cr4_mem_wr_en  ,cr3_mem_wr_en  ,cr2_mem_wr_en  ,cr1_mem_wr_en  ,cr0_mem_wr_en  };
wire [15:0]  crN_mem_rd_en   = {7'd0,   cr8_mem_rd_en  ,cr7_mem_rd_en  ,cr6_mem_rd_en  ,cr5_mem_rd_en  ,cr4_mem_rd_en  ,cr3_mem_rd_en  ,cr2_mem_rd_en  ,cr1_mem_rd_en  ,cr0_mem_rd_en  };
wire [15:0]  crN_mem_op_xtnd = {16'd0}; // No need to read extend for memory accesses (needed for ana registers)

wire [15:0]  crN_mem_ack;
wire [255:0] crN_mem_rd_data;

// Memory Arbiter
//
dwc_e12mp_phy_x4_ns_pcs_raw_arbt mem_arbt (
  // CR Clock and Reset
  .cr_clk           (cr_clk),
  .cr_rst           (cr_rst),

  // CR input interfaces
  .cr_req           (crN_mem_req),
  .cr_addr          (crN_mem_addr),
  .cr_wr_data       (crN_mem_wr_data),
  .cr_wr_en         (crN_mem_wr_en),
  .cr_rd_en         (crN_mem_rd_en),
  .cr_op_xtnd       (crN_mem_op_xtnd),
  .cr_ack           (crN_mem_ack),
  .cr_rd_data       (crN_mem_rd_data),
  `ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
  .sram_timing_en   (~sram_bypass),
  `endif

  // CR output interface
  .cr_arbt_addr     (cr_arbt_mem_addr),
  .cr_arbt_wr_en    (cr_arbt_mem_wr_en),
  .cr_arbt_wr_data  (cr_arbt_mem_wr_data),
  .cr_arbt_rd_en    (cr_arbt_mem_rd_en),
  .cr_arbt_rd_data  (cr_arbt_mem_rd_data)
);

assign cr0_mem_ack = crN_mem_ack[0];
assign cr1_mem_ack = crN_mem_ack[1];
assign cr2_mem_ack = crN_mem_ack[2];
assign cr3_mem_ack = crN_mem_ack[3];
assign cr4_mem_ack = crN_mem_ack[4];
assign cr5_mem_ack = crN_mem_ack[5];
assign cr6_mem_ack = crN_mem_ack[6];
assign cr7_mem_ack = crN_mem_ack[7];
assign cr8_mem_ack = crN_mem_ack[8];

assign cr0_mem_rd_data = crN_mem_rd_data[(16*1-1):(16*0)];
assign cr1_mem_rd_data = crN_mem_rd_data[(16*2-1):(16*1)];
assign cr2_mem_rd_data = crN_mem_rd_data[(16*3-1):(16*2)];
assign cr3_mem_rd_data = crN_mem_rd_data[(16*4-1):(16*3)];
assign cr4_mem_rd_data = crN_mem_rd_data[(16*5-1):(16*4)];
assign cr5_mem_rd_data = crN_mem_rd_data[(16*6-1):(16*5)];
assign cr6_mem_rd_data = crN_mem_rd_data[(16*7-1):(16*6)];
assign cr7_mem_rd_data = crN_mem_rd_data[(16*8-1):(16*7)];
assign cr8_mem_rd_data = crN_mem_rd_data[(16*9-1):(16*8)];

// -----------------------------------------------
// Build input buses to register arbiter
// -----------------------------------------------
// Assign external register requests to slot 8
assign cr8_reg_req        = cr_ext_reg_req;
assign cr8_reg_addr       = cr_ext_reg_addr;
assign cr8_reg_wr_en      = cr_ext_reg_wr_en;
assign cr8_reg_wr_data    = cr_ext_reg_wr_data;
assign cr8_reg_rd_en      = cr_ext_reg_rd_en;
assign cr_ext_reg_ack     = cr8_reg_ack;
assign cr_ext_reg_rd_data = cr8_reg_rd_data;

wire [15:0]  crN_reg_req     = {7'd0,  cr8_reg_req    ,cr7_reg_req    ,cr6_reg_req    ,cr5_reg_req    ,cr4_reg_req    ,cr3_reg_req    ,cr2_reg_req    ,cr1_reg_req    ,cr0_reg_req    };
wire [255:0] crN_reg_addr    = {112'd0,cr8_reg_addr   ,cr7_reg_addr   ,cr6_reg_addr   ,cr5_reg_addr   ,cr4_reg_addr   ,cr3_reg_addr   ,cr2_reg_addr   ,cr1_reg_addr   ,cr0_reg_addr   };
wire [255:0] crN_reg_wr_data = {112'd0,cr8_reg_wr_data,cr7_reg_wr_data,cr6_reg_wr_data,cr5_reg_wr_data,cr4_reg_wr_data,cr3_reg_wr_data,cr2_reg_wr_data,cr1_reg_wr_data,cr0_reg_wr_data};
wire [15:0]  crN_reg_wr_en   = {7'd0,  cr8_reg_wr_en  ,cr7_reg_wr_en  ,cr6_reg_wr_en  ,cr5_reg_wr_en  ,cr4_reg_wr_en  ,cr3_reg_wr_en  ,cr2_reg_wr_en  ,cr1_reg_wr_en  ,cr0_reg_wr_en  };
wire [15:0]  crN_reg_rd_en   = {7'd0,  cr8_reg_rd_en  ,cr7_reg_rd_en  ,cr6_reg_rd_en  ,cr5_reg_rd_en  ,cr4_reg_rd_en  ,cr3_reg_rd_en  ,cr2_reg_rd_en  ,cr1_reg_rd_en  ,cr0_reg_rd_en  };
// Mantis 6775 - only read extend for lanes when lane_fsm_op_xtnd_r is set (needed for ana registers)
wire [15:0]  crN_reg_op_xtnd = {7'd0,  1'b1           ,{8{lane_fsm_op_xtnd_r}}};

wire [15:0]  crN_reg_ack;
wire [255:0] crN_reg_rd_data;

// Combine read data for Register Arbiter
assign cr_arbt_reg_rd_data = cr_pma_rd_data |
                             cr0_rd_data    |
                             cr1_rd_data    |
                             cr2_rd_data    |
                             cr3_rd_data    |
                             cr4_rd_data    |
                             cr5_rd_data    |
                             cr6_rd_data    |
                             cr7_rd_data    |
                             cr_cmn_rd_data;

// Register Arbiter
//
dwc_e12mp_phy_x4_ns_pcs_raw_arbt reg_arbt (
  // CR Clock and Reset
  .cr_clk           (cr_clk),
  .cr_rst           (cr_rst),

  // CR input interfaces
  .cr_req           (crN_reg_req),
  .cr_addr          (crN_reg_addr),
  .cr_wr_data       (crN_reg_wr_data),
  .cr_wr_en         (crN_reg_wr_en),
  .cr_rd_en         (crN_reg_rd_en),
  .cr_op_xtnd       (crN_reg_op_xtnd),
  .cr_ack           (crN_reg_ack),
  .cr_rd_data       (crN_reg_rd_data),
  `ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
  .sram_timing_en   (1'b0),
  `endif
  
  // CR Interface output
  .cr_arbt_addr     (cr_arbt_reg_addr),
  .cr_arbt_wr_en    (cr_arbt_reg_wr_en),
  .cr_arbt_wr_data  (cr_arbt_reg_wr_data),
  .cr_arbt_rd_en    (cr_arbt_reg_rd_en),
  .cr_arbt_rd_data  (cr_arbt_reg_rd_data)
);

assign cr0_reg_ack = crN_reg_ack[0];
assign cr1_reg_ack = crN_reg_ack[1];
assign cr2_reg_ack = crN_reg_ack[2];
assign cr3_reg_ack = crN_reg_ack[3];
assign cr4_reg_ack = crN_reg_ack[4];
assign cr5_reg_ack = crN_reg_ack[5];
assign cr6_reg_ack = crN_reg_ack[6];
assign cr7_reg_ack = crN_reg_ack[7];
assign cr8_reg_ack = crN_reg_ack[8];

assign cr0_reg_rd_data = crN_reg_rd_data[(16*1-1):(16*0)];
assign cr1_reg_rd_data = crN_reg_rd_data[(16*2-1):(16*1)];
assign cr2_reg_rd_data = crN_reg_rd_data[(16*3-1):(16*2)];
assign cr3_reg_rd_data = crN_reg_rd_data[(16*4-1):(16*3)];
assign cr4_reg_rd_data = crN_reg_rd_data[(16*5-1):(16*4)];
assign cr5_reg_rd_data = crN_reg_rd_data[(16*6-1):(16*5)];
assign cr6_reg_rd_data = crN_reg_rd_data[(16*7-1):(16*6)];
assign cr7_reg_rd_data = crN_reg_rd_data[(16*8-1):(16*7)];
assign cr8_reg_rd_data = crN_reg_rd_data[(16*9-1):(16*8)];

`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
// Synchronize the sram_ext_ld_done signal to the cr_clk domain
wire sram_ext_ld_done_sync;
dwc_e12mp_phy_x4_ns_gen_sync sync_sram_ext_ld_done_cr_clk (
  .q   (sram_ext_ld_done_sync),
  .clk (cr_clk),
  .rst (cr_rst),
  .d   (sram_ext_ld_done)
);

// Create an sram_ext_ld_phase signal
wire sram_ext_ld_and1;
wire sram_ext_ld_phase;
dwc_e12mp_phy_x4_ns_gen_clk_and2 gen_sram_ext_ld_and1 (
  .out (sram_ext_ld_and1), 
  .clk (sram_init_done_out), 
  .en  (~sram_ext_ld_done_sync)
);

dwc_e12mp_phy_x4_ns_gen_clk_and2 gen_sram_ext_ld_phase (
  .out (sram_ext_ld_phase), 
  .clk (sram_ext_ld_and1), 
  .en  (~sram_bypass)
);

// Mantis 7141 - Drive ack signal when accessing SRAM during sram_ext_ld phase
// Ack for SRAM write is always 2cc
// Ack for SRAM read is always 3cc
// Mantis 7184 - Allow register access during SRAM external loading
// Register the read_en and write_en signals on the cr_clk to delay
// them to match the expected CR interface timing and to generate
// the appropriate ACKs
// Ack for REG write is always 2cc
// Ack for REG read is always 2cc

// Flop all incoming cr_ext_* signals so the appropriate delays
// can be set depending on whether an SRAM or REG access
// is being performed.
always @(posedge cr_clk or posedge cr_rst) begin
   if (cr_rst) begin
      cr_ext_wr_en_d   <= 1'b0;
      cr_ext_rd_en_d   <= 1'b0;
      cr_ext_rd_en_d2  <= 1'b0;
      cr_ext_addr_d    <= {`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}};
      cr_ext_wr_data_d <= {`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}};
      cr_ext_byp_ack   <= 1'b0;
   end else begin
      if (sram_ext_ld_phase) begin
         cr_ext_wr_en_d   <= cr_ext_wr_en;
         cr_ext_rd_en_d   <= cr_ext_rd_en;
         cr_ext_rd_en_d2  <= cr_ext_rd_en_d;
         cr_ext_addr_d    <= cr_ext_addr;
         cr_ext_wr_data_d <= cr_ext_wr_data;
         cr_ext_byp_ack <= cr_ext_byp_sram_ack | cr_ext_byp_reg_ack;
      end
   end
end

assign cr_ext_byp_sram_ack = sram_sel &
                             (cr_ext_wr_en_d | cr_ext_rd_en_d2);
assign cr_ext_byp_reg_ack  = ~sram_sel &
                             (cr_ext_wr_en_d | cr_ext_rd_en_d);

// Assign the cr_ext_ack signal to the arbiter
dwc_e12mp_phy_x4_ns_gen_mux cr_para_ack_mux (
  .out (cr_ext_ack),
  .sel (sram_ext_ld_phase),
  .d0  (cr_ext_arbt_ack),
  .d1  (cr_ext_byp_ack)
);

// MUX the outputs of the register arbiter with the external
// register requests during SRAM loading.
dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(1+1+`DWC_E12MP_X4NS_CR_ADDR_LEN+`DWC_E12MP_X4NS_CR_DATA_LEN))
cr_bus_mux (
  .out ({cr_rd_en_int,cr_wr_en_int,cr_addr_int,cr_wr_data_int}),
  .sel (sram_ext_ld_phase),
  .d0  ({cr_arbt_reg_rd_en,cr_arbt_reg_wr_en,cr_arbt_reg_addr,cr_arbt_reg_wr_data}),
  .d1  ({cr_ext_rd_en_d,cr_ext_wr_en_d,cr_ext_addr,cr_ext_wr_data})
);

`else
assign cr_addr_int    = cr_arbt_reg_addr;
assign cr_wr_data_int = cr_arbt_reg_wr_data;
assign cr_wr_en_int   = cr_arbt_reg_wr_en;
assign cr_rd_en_int   = cr_arbt_reg_rd_en;

`endif //DWC_E12MP_X4NS_SRAM_SUPPORT

// CREG parallel interface (for Raw PCS cmn/lane and PMA registers)
`ifdef ANI_SIM_GATES
// Delay cr bus to pma when ANI_SIM_GATES is defined
// 1.25ns equals 1/2 of smallest pulse width of cr_clk
// (200MHz pulse gated to 100MHz - so the pulse width is 2.5ns)
// This is needed because negedge of cr_clk is used in pma (for ana cregs)
assign #1.25 cr_addr     = cr_addr_int;
assign #1.25 cr_wr_data  = cr_wr_data_int;
assign #1.25 cr_wr_en    = cr_wr_en_int;
assign #1.25 cr_rd_en    = cr_rd_en_int;
`else
assign cr_addr     = cr_addr_int;
assign cr_wr_data  = cr_wr_data_int;
assign cr_wr_en    = cr_wr_en_int;
assign cr_rd_en    = cr_rd_en_int;
`endif

// -----------------------------------------------
// Raw PCS Memory
// -----------------------------------------------
dwc_e12mp_phy_x4_ns_pcs_raw_mem mem (
  
  // CREG parallel interface
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),

  .cr_cmn0_b0_sel        (cr_cmn0_b0_sel),
  .cr_cmn0_b1_sel        (cr_cmn0_b1_sel),
  .cr_cmn0_b2_sel        (cr_cmn0_b2_sel),
  .cr_cmn0_b3_sel        (cr_cmn0_b3_sel),
  .cr_cmn0_b4_sel        (cr_cmn0_b4_sel),
  .cr_cmn0_b5_sel        (cr_cmn0_b5_sel),
  .cr_cmn0_b6_sel        (cr_cmn0_b6_sel),
  .cr_cmn0_b7_sel        (cr_cmn0_b7_sel),
  
  .cr_cmn1_b0_sel        (cr_cmn1_b0_sel),
  .cr_cmn1_b1_sel        (cr_cmn1_b1_sel),
  .cr_cmn1_b2_sel        (cr_cmn1_b2_sel),
  .cr_cmn1_b3_sel        (cr_cmn1_b3_sel),
  .cr_cmn1_b4_sel        (cr_cmn1_b4_sel),
  .cr_cmn1_b5_sel        (cr_cmn1_b5_sel),
  .cr_cmn1_b6_sel        (cr_cmn1_b6_sel),
  .cr_cmn1_b7_sel        (cr_cmn1_b7_sel),
 
  .cr_cmn2_b0_sel        (cr_cmn2_b0_sel),
  .cr_cmn2_b1_sel        (cr_cmn2_b1_sel),
  .cr_cmn2_b2_sel        (cr_cmn2_b2_sel),
  .cr_cmn2_b3_sel        (cr_cmn2_b3_sel),
  .cr_cmn2_b4_sel        (cr_cmn2_b4_sel),
  .cr_cmn2_b5_sel        (cr_cmn2_b5_sel),
  .cr_cmn2_b6_sel        (cr_cmn2_b6_sel),
  .cr_cmn2_b7_sel        (cr_cmn2_b7_sel),

  .cr_cmn3_b0_sel        (cr_cmn3_b0_sel),
  .cr_cmn3_b1_sel        (cr_cmn3_b1_sel),
  .cr_cmn3_b2_sel        (cr_cmn3_b2_sel),
  .cr_cmn3_b3_sel        (cr_cmn3_b3_sel),
  .cr_cmn3_b4_sel        (cr_cmn3_b4_sel),
  .cr_cmn3_b5_sel        (cr_cmn3_b5_sel),
  .cr_cmn3_b6_sel        (cr_cmn3_b6_sel),
  .cr_cmn3_b7_sel        (cr_cmn3_b7_sel),

  .cr_cmn4_b0_sel        (cr_cmn4_b0_sel),
  .cr_cmn4_b1_sel        (cr_cmn4_b1_sel),
  .cr_cmn4_b2_sel        (cr_cmn4_b2_sel),
  .cr_cmn4_b3_sel        (cr_cmn4_b3_sel),
  .cr_cmn4_b4_sel        (cr_cmn4_b4_sel),
  .cr_cmn4_b5_sel        (cr_cmn4_b5_sel),
  .cr_cmn4_b6_sel        (cr_cmn4_b6_sel),
  .cr_cmn4_b7_sel        (cr_cmn4_b7_sel),

  .cr_cmn5_b0_sel        (cr_cmn5_b0_sel),
  .cr_cmn5_b1_sel        (cr_cmn5_b1_sel),
  .cr_cmn5_b2_sel        (cr_cmn5_b2_sel),
  .cr_cmn5_b3_sel        (cr_cmn5_b3_sel),
  .cr_cmn5_b4_sel        (cr_cmn5_b4_sel),
  .cr_cmn5_b5_sel        (cr_cmn5_b5_sel),
  .cr_cmn5_b6_sel        (cr_cmn5_b6_sel),
  .cr_cmn5_b7_sel        (cr_cmn5_b7_sel),

  .cr_cmn6_b0_sel        (cr_cmn6_b0_sel),
  .cr_cmn6_b1_sel        (cr_cmn6_b1_sel),
  .cr_cmn6_b2_sel        (cr_cmn6_b2_sel),
  .cr_cmn6_b3_sel        (cr_cmn6_b3_sel),
  .cr_cmn6_b4_sel        (cr_cmn6_b4_sel),
  .cr_cmn6_b5_sel        (cr_cmn6_b5_sel),
  .cr_cmn6_b6_sel        (cr_cmn6_b6_sel),
  .cr_cmn6_b7_sel        (cr_cmn6_b7_sel),

  .cr_cmn7_b0_sel        (cr_cmn7_b0_sel),
  .cr_cmn7_b1_sel        (cr_cmn7_b1_sel),
  .cr_cmn7_b2_sel        (cr_cmn7_b2_sel),
  .cr_cmn7_b3_sel        (cr_cmn7_b3_sel),
  .cr_cmn7_b4_sel        (cr_cmn7_b4_sel),
  .cr_cmn7_b5_sel        (cr_cmn7_b5_sel),
  .cr_cmn7_b6_sel        (cr_cmn7_b6_sel),
  .cr_cmn7_b7_sel        (cr_cmn7_b7_sel),

  .cr_cmn8_b0_sel        (cr_cmn8_b0_sel),
  .cr_cmn8_b1_sel        (cr_cmn8_b1_sel),
  .cr_cmn8_b2_sel        (cr_cmn8_b2_sel),
  .cr_cmn8_b3_sel        (cr_cmn8_b3_sel),
  .cr_cmn8_b4_sel        (cr_cmn8_b4_sel),
  .cr_cmn8_b5_sel        (cr_cmn8_b5_sel),
  .cr_cmn8_b6_sel        (cr_cmn8_b6_sel),
  .cr_cmn8_b7_sel        (cr_cmn8_b7_sel),

  .cr_cmn9_b0_sel        (cr_cmn9_b0_sel),
  .cr_cmn9_b1_sel        (cr_cmn9_b1_sel),
  .cr_cmn9_b2_sel        (cr_cmn9_b2_sel),
  .cr_cmn9_b3_sel        (cr_cmn9_b3_sel),
  .cr_cmn9_b4_sel        (cr_cmn9_b4_sel),
  .cr_cmn9_b5_sel        (cr_cmn9_b5_sel),
  .cr_cmn9_b6_sel        (cr_cmn9_b6_sel),
  .cr_cmn9_b7_sel        (cr_cmn9_b7_sel),

  .cr_cmn10_b0_sel       (cr_cmn10_b0_sel),
  .cr_cmn10_b1_sel       (cr_cmn10_b1_sel),
  .cr_cmn10_b2_sel       (cr_cmn10_b2_sel),
  .cr_cmn10_b3_sel       (cr_cmn10_b3_sel),
  .cr_cmn10_b4_sel       (cr_cmn10_b4_sel),
  .cr_cmn10_b5_sel       (cr_cmn10_b5_sel),
  .cr_cmn10_b6_sel       (cr_cmn10_b6_sel),
  .cr_cmn10_b7_sel       (cr_cmn10_b7_sel),

  .cr_cmn11_b0_sel       (cr_cmn11_b0_sel),
  .cr_cmn11_b1_sel       (cr_cmn11_b1_sel),
  .cr_cmn11_b2_sel       (cr_cmn11_b2_sel),
  .cr_cmn11_b3_sel       (cr_cmn11_b3_sel),
  .cr_cmn11_b4_sel       (cr_cmn11_b4_sel),
  .cr_cmn11_b5_sel       (cr_cmn11_b5_sel),
  .cr_cmn11_b6_sel       (cr_cmn11_b6_sel),
  .cr_cmn11_b7_sel       (cr_cmn11_b7_sel),

  .cr_cmn12_b0_sel       (cr_cmn12_b0_sel),
  .cr_cmn12_b1_sel       (cr_cmn12_b1_sel),
  .cr_cmn12_b2_sel       (cr_cmn12_b2_sel),
  .cr_cmn12_b3_sel       (cr_cmn12_b3_sel),
  .cr_cmn12_b4_sel       (cr_cmn12_b4_sel),
  .cr_cmn12_b5_sel       (cr_cmn12_b5_sel),
  .cr_cmn12_b6_sel       (cr_cmn12_b6_sel),
  .cr_cmn12_b7_sel       (cr_cmn12_b7_sel),

  .cr_cmn13_b0_sel       (cr_cmn13_b0_sel),
  .cr_cmn13_b1_sel       (cr_cmn13_b1_sel),
  .cr_cmn13_b2_sel       (cr_cmn13_b2_sel),
  .cr_cmn13_b3_sel       (cr_cmn13_b3_sel),
  .cr_cmn13_b4_sel       (cr_cmn13_b4_sel),
  .cr_cmn13_b5_sel       (cr_cmn13_b5_sel),
  .cr_cmn13_b6_sel       (cr_cmn13_b6_sel),
  .cr_cmn13_b7_sel       (cr_cmn13_b7_sel),

  .cr_cmn14_b0_sel       (cr_cmn14_b0_sel),
  .cr_cmn14_b1_sel       (cr_cmn14_b1_sel),
  .cr_cmn14_b2_sel       (cr_cmn14_b2_sel),
  .cr_cmn14_b3_sel       (cr_cmn14_b3_sel),
  .cr_cmn14_b4_sel       (cr_cmn14_b4_sel),
  .cr_cmn14_b5_sel       (cr_cmn14_b5_sel),
  .cr_cmn14_b6_sel       (cr_cmn14_b6_sel),
  .cr_cmn14_b7_sel       (cr_cmn14_b7_sel),

  .cr_cmn15_b0_sel       (cr_cmn15_b0_sel),
  .cr_cmn15_b1_sel       (cr_cmn15_b1_sel),
  .cr_cmn15_b2_sel       (cr_cmn15_b2_sel),
  .cr_cmn15_b3_sel       (cr_cmn15_b3_sel),
  .cr_cmn15_b4_sel       (cr_cmn15_b4_sel),
  .cr_cmn15_b5_sel       (cr_cmn15_b5_sel),
  .cr_cmn15_b6_sel       (cr_cmn15_b6_sel),
  .cr_cmn15_b7_sel       (cr_cmn15_b7_sel),

  .prgm_size             (prgm_size),

  .cr_wr_en              (cr_mem_wr_en),
  .cr_wr_data            (cr_mem_wr_data),
  .cr_rd_en              (cr_mem_rd_en),
  .cr_rd_data            (cr_mem_rd_data)
);

// -----------------------------------------------
// Control register select generation
// -----------------------------------------------
dwc_e12mp_phy_x4_ns_pcs_raw_mem_decode #(.CR_TYPE(`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_ROM0)) mem_creg (

  // CREG interface
  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_mem_addr),
  
  // CMN0
  .cr_cmn0_b0_sel        (cr_cmn0_b0_sel),
  .cr_cmn0_b1_sel        (cr_cmn0_b1_sel),
  .cr_cmn0_b2_sel        (cr_cmn0_b2_sel),
  .cr_cmn0_b3_sel        (cr_cmn0_b3_sel),
  .cr_cmn0_b4_sel        (cr_cmn0_b4_sel),
  .cr_cmn0_b5_sel        (cr_cmn0_b5_sel),
  .cr_cmn0_b6_sel        (cr_cmn0_b6_sel),
  .cr_cmn0_b7_sel        (cr_cmn0_b7_sel),

  // CMN1
  .cr_cmn1_b0_sel        (cr_cmn1_b0_sel),
  .cr_cmn1_b1_sel        (cr_cmn1_b1_sel),
  .cr_cmn1_b2_sel        (cr_cmn1_b2_sel),
  .cr_cmn1_b3_sel        (cr_cmn1_b3_sel),
  .cr_cmn1_b4_sel        (cr_cmn1_b4_sel),
  .cr_cmn1_b5_sel        (cr_cmn1_b5_sel),
  .cr_cmn1_b6_sel        (cr_cmn1_b6_sel),
  .cr_cmn1_b7_sel        (cr_cmn1_b7_sel),

  // CMN2
  .cr_cmn2_b0_sel        (cr_cmn2_b0_sel),
  .cr_cmn2_b1_sel        (cr_cmn2_b1_sel),
  .cr_cmn2_b2_sel        (cr_cmn2_b2_sel),
  .cr_cmn2_b3_sel        (cr_cmn2_b3_sel),
  .cr_cmn2_b4_sel        (cr_cmn2_b4_sel),
  .cr_cmn2_b5_sel        (cr_cmn2_b5_sel),
  .cr_cmn2_b6_sel        (cr_cmn2_b6_sel),
  .cr_cmn2_b7_sel        (cr_cmn2_b7_sel),

  // CMN3
  .cr_cmn3_b0_sel        (cr_cmn3_b0_sel),
  .cr_cmn3_b1_sel        (cr_cmn3_b1_sel),
  .cr_cmn3_b2_sel        (cr_cmn3_b2_sel),
  .cr_cmn3_b3_sel        (cr_cmn3_b3_sel),
  .cr_cmn3_b4_sel        (cr_cmn3_b4_sel),
  .cr_cmn3_b5_sel        (cr_cmn3_b5_sel),
  .cr_cmn3_b6_sel        (cr_cmn3_b6_sel),
  .cr_cmn3_b7_sel        (cr_cmn3_b7_sel),

  // CMN4
  .cr_cmn4_b0_sel        (cr_cmn4_b0_sel),
  .cr_cmn4_b1_sel        (cr_cmn4_b1_sel),
  .cr_cmn4_b2_sel        (cr_cmn4_b2_sel),
  .cr_cmn4_b3_sel        (cr_cmn4_b3_sel),
  .cr_cmn4_b4_sel        (cr_cmn4_b4_sel),
  .cr_cmn4_b5_sel        (cr_cmn4_b5_sel),
  .cr_cmn4_b6_sel        (cr_cmn4_b6_sel),
  .cr_cmn4_b7_sel        (cr_cmn4_b7_sel),

  // CMN5
  .cr_cmn5_b0_sel        (cr_cmn5_b0_sel),
  .cr_cmn5_b1_sel        (cr_cmn5_b1_sel),
  .cr_cmn5_b2_sel        (cr_cmn5_b2_sel),
  .cr_cmn5_b3_sel        (cr_cmn5_b3_sel),
  .cr_cmn5_b4_sel        (cr_cmn5_b4_sel),
  .cr_cmn5_b5_sel        (cr_cmn5_b5_sel),
  .cr_cmn5_b6_sel        (cr_cmn5_b6_sel),
  .cr_cmn5_b7_sel        (cr_cmn5_b7_sel),

  // CMN6
  .cr_cmn6_b0_sel        (cr_cmn6_b0_sel),
  .cr_cmn6_b1_sel        (cr_cmn6_b1_sel),
  .cr_cmn6_b2_sel        (cr_cmn6_b2_sel),
  .cr_cmn6_b3_sel        (cr_cmn6_b3_sel),
  .cr_cmn6_b4_sel        (cr_cmn6_b4_sel),
  .cr_cmn6_b5_sel        (cr_cmn6_b5_sel),
  .cr_cmn6_b6_sel        (cr_cmn6_b6_sel),
  .cr_cmn6_b7_sel        (cr_cmn6_b7_sel),

  // CMN7
  .cr_cmn7_b0_sel        (cr_cmn7_b0_sel),
  .cr_cmn7_b1_sel        (cr_cmn7_b1_sel),
  .cr_cmn7_b2_sel        (cr_cmn7_b2_sel),
  .cr_cmn7_b3_sel        (cr_cmn7_b3_sel),
  .cr_cmn7_b4_sel        (cr_cmn7_b4_sel),
  .cr_cmn7_b5_sel        (cr_cmn7_b5_sel),
  .cr_cmn7_b6_sel        (cr_cmn7_b6_sel),
  .cr_cmn7_b7_sel        (cr_cmn7_b7_sel),

  // CMN8
  .cr_cmn8_b0_sel        (cr_cmn8_b0_sel),
  .cr_cmn8_b1_sel        (cr_cmn8_b1_sel),
  .cr_cmn8_b2_sel        (cr_cmn8_b2_sel),
  .cr_cmn8_b3_sel        (cr_cmn8_b3_sel),
  .cr_cmn8_b4_sel        (cr_cmn8_b4_sel),
  .cr_cmn8_b5_sel        (cr_cmn8_b5_sel),
  .cr_cmn8_b6_sel        (cr_cmn8_b6_sel),
  .cr_cmn8_b7_sel        (cr_cmn8_b7_sel),

  // CMN9
  .cr_cmn9_b0_sel        (cr_cmn9_b0_sel),
  .cr_cmn9_b1_sel        (cr_cmn9_b1_sel),
  .cr_cmn9_b2_sel        (cr_cmn9_b2_sel),
  .cr_cmn9_b3_sel        (cr_cmn9_b3_sel),
  .cr_cmn9_b4_sel        (cr_cmn9_b4_sel),
  .cr_cmn9_b5_sel        (cr_cmn9_b5_sel),
  .cr_cmn9_b6_sel        (cr_cmn9_b6_sel),
  .cr_cmn9_b7_sel        (cr_cmn9_b7_sel),

  // CMN10
  .cr_cmn10_b0_sel       (cr_cmn10_b0_sel),
  .cr_cmn10_b1_sel       (cr_cmn10_b1_sel),
  .cr_cmn10_b2_sel       (cr_cmn10_b2_sel),
  .cr_cmn10_b3_sel       (cr_cmn10_b3_sel),
  .cr_cmn10_b4_sel       (cr_cmn10_b4_sel),
  .cr_cmn10_b5_sel       (cr_cmn10_b5_sel),
  .cr_cmn10_b6_sel       (cr_cmn10_b6_sel),
  .cr_cmn10_b7_sel       (cr_cmn10_b7_sel),

  // CMN11
  .cr_cmn11_b0_sel       (cr_cmn11_b0_sel),
  .cr_cmn11_b1_sel       (cr_cmn11_b1_sel),
  .cr_cmn11_b2_sel       (cr_cmn11_b2_sel),
  .cr_cmn11_b3_sel       (cr_cmn11_b3_sel),
  .cr_cmn11_b4_sel       (cr_cmn11_b4_sel),
  .cr_cmn11_b5_sel       (cr_cmn11_b5_sel),
  .cr_cmn11_b6_sel       (cr_cmn11_b6_sel),
  .cr_cmn11_b7_sel       (cr_cmn11_b7_sel),

  // CMN12
  .cr_cmn12_b0_sel       (cr_cmn12_b0_sel),
  .cr_cmn12_b1_sel       (cr_cmn12_b1_sel),
  .cr_cmn12_b2_sel       (cr_cmn12_b2_sel),
  .cr_cmn12_b3_sel       (cr_cmn12_b3_sel),
  .cr_cmn12_b4_sel       (cr_cmn12_b4_sel),
  .cr_cmn12_b5_sel       (cr_cmn12_b5_sel),
  .cr_cmn12_b6_sel       (cr_cmn12_b6_sel),
  .cr_cmn12_b7_sel       (cr_cmn12_b7_sel),

  // CMN13
  .cr_cmn13_b0_sel       (cr_cmn13_b0_sel),
  .cr_cmn13_b1_sel       (cr_cmn13_b1_sel),
  .cr_cmn13_b2_sel       (cr_cmn13_b2_sel),
  .cr_cmn13_b3_sel       (cr_cmn13_b3_sel),
  .cr_cmn13_b4_sel       (cr_cmn13_b4_sel),
  .cr_cmn13_b5_sel       (cr_cmn13_b5_sel),
  .cr_cmn13_b6_sel       (cr_cmn13_b6_sel),
  .cr_cmn13_b7_sel       (cr_cmn13_b7_sel),

  // CMN14
  .cr_cmn14_b0_sel       (cr_cmn14_b0_sel),
  .cr_cmn14_b1_sel       (cr_cmn14_b1_sel),
  .cr_cmn14_b2_sel       (cr_cmn14_b2_sel),
  .cr_cmn14_b3_sel       (cr_cmn14_b3_sel),
  .cr_cmn14_b4_sel       (cr_cmn14_b4_sel),
  .cr_cmn14_b5_sel       (cr_cmn14_b5_sel),
  .cr_cmn14_b6_sel       (cr_cmn14_b6_sel),
  .cr_cmn14_b7_sel       (cr_cmn14_b7_sel),

  // CMN15
  .cr_cmn15_b0_sel       (cr_cmn15_b0_sel),
  .cr_cmn15_b1_sel       (cr_cmn15_b1_sel),
  .cr_cmn15_b2_sel       (cr_cmn15_b2_sel),
  .cr_cmn15_b3_sel       (cr_cmn15_b3_sel),
  .cr_cmn15_b4_sel       (cr_cmn15_b4_sel),
  .cr_cmn15_b5_sel       (cr_cmn15_b5_sel),
  .cr_cmn15_b6_sel       (cr_cmn15_b6_sel),
  .cr_cmn15_b7_sel       (cr_cmn15_b7_sel)

);

`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
// -----------------------------------------------
// SRAM Bootloader
// -----------------------------------------------
dwc_e12mp_phy_x4_ns_pcs_raw_sram_bootloader bootloader (
   // Clocks and resets
   .cr_clk             (cr_clk),
   .cr_rst             (cr_rst),
   // Control inputs
   .sram_bypass        (sram_bypass),
   .sram_init_done_in  (sram_init_done_in),
   .prgm_size          (prgm_size),
   // Control outputs
   .sram_init_done_out (sram_init_done_out),
   // ROM interface
   .cr_mem_rd_en       (cr_mem_rd_en_bl),
   .cr_mem_addr        (cr_mem_addr_bl),
   .cr_mem_rd_data     (cr_mem_rd_data),
   // SRAM interface   
   .sram_wr_en         (sram_wr_en_bl),
   .sram_addr          (sram_addr_bl),
   .sram_wr_data       (sram_wr_data_bl)
);

// Generate a fw_rdy signal once the bootloader is complete.
// Wait for sram_init_done_out and sram_ext_ld_done to be asserted,
// as well as the sram GLCM to have settled to the cr_clk

// Create an sram_rdy signal to denote the completion of
// bootloading and external loading
wire sram_rdy_and1;
wire sram_rdy;
dwc_e12mp_phy_x4_ns_gen_clk_and2 gen_sram_rdy_and1 (
  .out (sram_rdy_and1), 
  .clk (sram_init_done_out), 
  .en  (sram_ext_ld_done_sync)
);

dwc_e12mp_phy_x4_ns_pcs_raw_gen_clk_or2 gen_sram_rdy (
  .out  (sram_rdy), 
  .clk1 (sram_rdy_and1), 
  .clk2 (sram_bypass)
);

assign fw_rdy = sram_rdy;

// Mantis 7147 - Remove fixed muxing and connect both ROM and RAM so they can
// both be accessed
// CR signal muxing to ROM
// First stage of muxing between the CR data from the bootloader
// and the external CR para interface
dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(1+1+`DWC_E12MP_X4NS_CR_ADDR_LEN+`DWC_E12MP_X4NS_CR_DATA_LEN+`DWC_E12MP_X4NS_CR_DATA_LEN))
cr_mem_mux1 (
  .out ({cr_mem_rd_en_int,cr_mem_wr_en_int,cr_mem_addr_int,cr_mem_wr_data_int,cr_mem_rd_data_int}),
  .sel (sram_ext_ld_phase),
  .d0  ({cr_mem_rd_en_bl,1'b0,cr_mem_addr_bl,{`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}},{`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}}}),
  .d1  ({cr_rd_en,cr_wr_en,cr_addr,cr_wr_data,cr_arbt_mem_rd_data_or})
);

// Second stage of muxing between the first stage and the default
// connection of the memory arbiter to the ROM
dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(1+1+`DWC_E12MP_X4NS_CR_ADDR_LEN+`DWC_E12MP_X4NS_CR_DATA_LEN+`DWC_E12MP_X4NS_CR_DATA_LEN))
cr_mem_mux2 (
  .out ({cr_mem_rd_en,cr_mem_wr_en,cr_mem_addr,cr_mem_wr_data,cr_arbt_mem_rd_data}),
  .sel (sram_rdy),
  .d0  ({cr_mem_rd_en_int,cr_mem_wr_en_int,cr_mem_addr_int,cr_mem_wr_data_int,cr_mem_rd_data_int}),
  .d1  ({cr_arbt_mem_rd_en,cr_arbt_mem_wr_en,cr_arbt_mem_addr,cr_arbt_mem_wr_data,cr_arbt_mem_rd_data_or})
);

// OR the mem read data with the gated sram_rd_data
assign cr_arbt_mem_rd_data_or = cr_mem_rd_data | (sram_rd_data & {`DWC_E12MP_X4NS_CR_DATA_LEN{sram_rd_data_vld}});

// Create gating signals to control when the SRAM can be
// accessed.  Since there is no external address decoding
// for the SRAM, gate the signals to the SRAM when the
// type doesnt match.  Also mux incoming sram data
// such that it is always zero when the SRAM is not being
// accessed
assign sram_ext_sel = (cr_ext_addr_d[`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RANGE] == `DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RAM0) |
                      (cr_ext_addr_d[`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RANGE] == `DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RAM1);

// Create gating signals to control whether SRAM or ROM is
// being read by the memory arbiter
assign sram_int_sel = cr_arbt_mem_wr_en ?
                        ((cr_arbt_mem_addr_d[`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RANGE] == `DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RAM0) |
                         (cr_arbt_mem_addr_d[`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RANGE] == `DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RAM1))  :
                        ((cr_arbt_mem_addr[`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RANGE] == `DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RAM0)   |
                         (cr_arbt_mem_addr[`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RANGE] == `DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_RAM1));

dwc_e12mp_phy_x4_ns_gen_mux sram_sel_mux (
  .out (sram_sel_int),
  .sel (sram_ext_ld_phase),
  .d0  (sram_int_sel),
  .d1  (sram_ext_sel)
);

// Always gate the sram_sel signal when sram_bypass is asserted
dwc_e12mp_phy_x4_ns_gen_clk_and2 sram_sel_and (
  .out (sram_sel), 
  .clk (sram_sel_int),
  .en  (~sram_bypass)
);

// Flop the signal to align it with SRAM read data
// Also flop the write address from the memory arbiter
// going to the SRAM to align it with the wr_en and
// wr_data.  Also flop the incoming sram rd data
// to break the timing path during external
// loading phase
always @(posedge cr_clk or posedge cr_rst) begin
   if (cr_rst) begin
      sram_rd_data_d     <= {`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}};
      sram_rd_data_vld   <= 0;
      cr_arbt_mem_addr_d <= {`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}};
   end else begin
      sram_rd_data_d     <= sram_rd_data;
      sram_rd_data_vld   <= sram_sel;
      cr_arbt_mem_addr_d <= cr_arbt_mem_addr;
   end
end

assign sram_rd_data_gated = sram_rd_data_d & {`DWC_E12MP_X4NS_CR_DATA_LEN{sram_sel}}; 
   
// Muxing to SRAM
// First stage of muxing between the SRAM data from the bootloader
// and the external CR para interface
assign sram_rd_en_ext_ld     = cr_ext_rd_en_d & sram_sel;
assign sram_wr_en_ext_ld     = cr_ext_wr_en_d & sram_sel;
assign sram_addr_ext_ld      = cr_ext_addr_d[`DWC_E12MP_X4NS_SRAM_ADDR_RANGE];
assign sram_wr_data_ext_ld   = cr_ext_wr_data_d;
assign cr_ext_rd_data_ext_ld = cr_arbt_reg_rd_data | cr_mem_rd_data | sram_rd_data_gated;
dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(1+1+`DWC_E12MP_X4NS_SRAM_ADDR_LEN+`DWC_E12MP_X4NS_CR_DATA_LEN+`DWC_E12MP_X4NS_CR_DATA_LEN))
sram_mux1 (
  .out ({sram_rd_en_int1,sram_wr_en_int1,sram_addr_int1,sram_wr_data_int1,cr_ext_rd_data_int1}),
  .sel (sram_ext_ld_phase),
  .d0  ({1'b0,sram_wr_en_bl,sram_addr_bl,sram_wr_data_bl,{`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}}}),
  .d1  ({sram_rd_en_ext_ld,sram_wr_en_ext_ld,sram_addr_ext_ld,sram_wr_data_ext_ld,cr_ext_rd_data_ext_ld})
);

// Second stage of muxing between the first stage and the default
// connection of the memory arbiter to the SRAM
assign sram_rd_en_arbt     = cr_arbt_mem_rd_en & sram_sel;
assign sram_wr_en_arbt     = cr_arbt_mem_wr_en & sram_sel;
assign sram_addr_arbt      = cr_arbt_mem_wr_en ? cr_arbt_mem_addr_d : cr_arbt_mem_addr;
assign sram_wr_data_arbt   = cr_arbt_mem_wr_data;
dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(1+1+`DWC_E12MP_X4NS_SRAM_ADDR_LEN+`DWC_E12MP_X4NS_CR_DATA_LEN+`DWC_E12MP_X4NS_CR_DATA_LEN))
sram_mux2 (
  .out ({sram_rd_en_int2,sram_wr_en_int2,sram_addr_int2,sram_wr_data_int2,cr_ext_rd_data_int2}),
  .sel (sram_rdy),
  .d0  ({sram_rd_en_int1,sram_wr_en_int1,sram_addr_int1,sram_wr_data_int1,cr_ext_rd_data_int1}),
  .d1  ({sram_rd_en_arbt,sram_wr_en_arbt,sram_addr_arbt,sram_wr_data_arbt,cr_ext_rd_data_arbt})
);

// Third stage of muxing between the second stage and sram_bypass mode
dwc_e12mp_phy_x4_ns_gen_mux #(.WIDTH(1+1+`DWC_E12MP_X4NS_SRAM_ADDR_LEN+`DWC_E12MP_X4NS_CR_DATA_LEN+`DWC_E12MP_X4NS_CR_DATA_LEN))
sram_mux3 (
  .out ({sram_rd_en,sram_wr_en,sram_addr,sram_wr_data,cr_ext_rd_data}),
  .sel (sram_bypass),
  .d0  ({sram_rd_en_int2,sram_wr_en_int2,sram_addr_int2,sram_wr_data_int2,cr_ext_rd_data_int2}),
  .d1  ({1'b0,1'b0,{`DWC_E12MP_X4NS_SRAM_ADDR_LEN{1'b0}},{`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}},cr_ext_rd_data_arbt})
);

// Mantis 7174 - Use cr_clk as sram_clk
// Assign the sram_clk output to cr_clk
assign sram_clk = cr_clk;

`ifdef DWC_FPGA_MODE
wire fpga_ext_clk_sel = sram_init_done_out & ~sram_ext_ld_done;

// Delay cr_clk_rdy by a few cycles to ensure that fw_rdy is not signaled
// before the clock mux has switched over to cr_clk from cr_ext_clk

localparam stBOOTLD = 2'd0;
localparam stEXTLD  = 2'd1;
localparam stEXTLD2 = 2'd2;
localparam stNORMOP = 2'd3;

reg [1:0] state;
reg [6:0] extld_cnt;

always @(posedge cr_clk or posedge cr_rst) begin
 if (cr_rst) begin
  state     <= stBOOTLD;
  extld_cnt <= 0;
 end else begin
  case (state)
   stBOOTLD: begin
              if (sram_init_done_out & ~sram_ext_ld_done_sync) begin
               state <= stEXTLD;
              end else if (sram_init_done_out & sram_ext_ld_done_sync) begin
               // In the current FPGA implementation, this condition should not be reached,
       	// but is being included to ensure that the FSM does not get stuck
               state <= stNORMOP;
              end
             end
             
   stEXTLD:  begin
              if (sram_init_done_out & sram_ext_ld_done_sync) begin
               state <= stEXTLD2;
              end
             end

   stEXTLD2: begin
              // Bufgmux switches over in max 3 slow clock cycles
              // Convert this to the fast clock's cycles, and add some margin
              extld_cnt <= extld_cnt + 7'd1;
              if (extld_cnt == 7'd127) begin
               state <= stNORMOP;
              end
             end
             
   stNORMOP: begin
              if (sram_init_done_out & ~sram_ext_ld_done_sync) begin
               state <= stEXTLD;
              end
             end	      
  endcase
 end
end

wire cr_clk_rdy = (state == stBOOTLD) | (state == stNORMOP);

`endif //DWC_FPGA_MODE

`else // DWC_E12MP_X4NS_SRAM_SUPPORT

// Firmware is always ready
assign fw_rdy = 1'b1;

// Connect memory aribter IO's to ROM
assign cr_mem_rd_en        = cr_arbt_mem_rd_en;
assign cr_mem_wr_en        = cr_arbt_mem_wr_en;
assign cr_mem_addr         = cr_arbt_mem_addr;
assign cr_mem_wr_data      = cr_arbt_mem_wr_data;
assign cr_arbt_mem_rd_data = cr_mem_rd_data;

// Connect the external read interface to the external arbiter
assign cr_ext_rd_data = cr_ext_rd_data_arbt;

// Assign the cr_ext_ack signal to the arbiter
assign cr_ext_ack = cr_ext_arbt_ack;

`endif // DWC_E12MP_X4NS_SRAM_SUPPORT

// Control register select generation
//
dwc_e12mp_phy_x4_ns_pcs_raw_cmn_creg cmn_creg (
  .cr_cmn_sel            (cr_cmn_sel),
  .cr_cmn_aon_sel        (cr_cmn_aon_sel),

  .cr_clk                (cr_clk),
  .cr_rst                (cr_rst),
  .cr_addr               (cr_addr)
);

// %%CREG_BLOCK AON - pcs_raw_aon_cmn(0x20)
//
// This block is instantiated under pcs_raw_aon_xN
// but keeping creg block comment here to indicate
// the block's address
//pcs_raw_aon_cmn aon_cmn (

// ---------------------------------------------------------------------
// %%CREG CMN_CTL - Common control register
//   OFFSET: 0x00
//   ATTR: READ,WRITE
//   FIELDS:
//      [0] PHY_FUNC_RST   - Resets the PHY except registers in the Raw PCS common and always-on registers.
//          NOTES:           Useful for resetting the PHY after reloading the
//                           Memory and without resetting the Memory.
//          RESET: 0x0
//
// ---------------------------------------------------------------------
wire        phy_func_reset_r;
wire [15:0] cr_cmn_ctl_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(`DWC_PHY_FUNC_RST_INIT_VAL), .MSK_VAL(1'b0)) 
 cmn_ctl_reg (
  .cr_val      ({
                 phy_func_reset_r
                 }),
  .cr_rd_data  (cr_cmn_ctl_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_cmn_sel[0]),
  .cr_self_clr (1'b0)
);

// Output functional-mode reset to Always On block
assign phy_func_reset = phy_func_reset_r;

// ---------------------------------------------------------------------
// %%CREG MPLLA_BW_OVRD_IN - Override values for incoming MPLLA bandwidth
//   OFFSET: 0x01
//   ATTR: READ,WRITE
//   FIELDS:
//    [11] MPLLA_BW_OVRD_EN  - Override enable for mplla_bandwidth[10:0]
//         RESET: 0x0
//  [10:0] MPLLA_BW_OVRD_VAL - Override value for mplla_bandwidth[10:0]
//         RESET: 0x43
//
// ---------------------------------------------------------------------
wire        mplla_bandwidth_ovrd_en_r;
wire [10:0] mplla_bandwidth_ovrd_val_r;
wire [15:0] mplla_bw_ovrd_in_rd_data;

dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(12), .RST_VAL(12'b0_00001000011), .MSK_VAL(12'd0))
 mplla_bw_ovrd_in_reg (
  .cr_val      ({
                 mplla_bandwidth_ovrd_en_r,
                 mplla_bandwidth_ovrd_val_r
                }),
  .cr_rd_data  (mplla_bw_ovrd_in_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_cmn_sel[1]),
  .cr_self_clr (1'b0)
);

// ---------------------------------------------------------------------
// %%CREG MPLLA_SSC_CTL_OVRD_IN - Override values for incoming MPLLA SSC control settings
//   OFFSET: 0x02
//   ATTR: READ,WRITE
//   FIELDS:
//     [15] MPLLA_SSC_CTL_OVRD_EN  - Override value for MPLLA SSC control settings
//          RESET: 0x0
//  [14:12] MPLLA_SSC_CLK_SEL      - Override value for mplla_ssc_clk_sel[2:0]
//          RESET: 0x5
//   [11:3] MPLLA_FRACN_CTRL       - Override value for mplla_fracn_ctrl[8:0]
//          RESET: 0x0
//    [2:0] MPLLA_SSC_RANGE        - Override value for mplla_ssc_range[2:0]
//          RESET: 0x0
//
// ---------------------------------------------------------------------
wire        mplla_ssc_ctl_ovrd_en_r;
wire [2:0]  mplla_ssc_clk_sel_r;
wire [8:0]  mplla_fracn_ctrl_r;
wire [2:0]  mplla_ssc_range_r;
wire [15:0] mplla_ssc_ctl_ovrd_in_rd_data;

dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'b0_101_000000000_000), .MSK_VAL(16'd0))
 mplla_ssc_ctl_ovrd_in_reg (
  .cr_val      ({
                 mplla_ssc_ctl_ovrd_en_r,
                 mplla_ssc_clk_sel_r,
                 mplla_fracn_ctrl_r,
                 mplla_ssc_range_r
                }),
  .cr_rd_data  (mplla_ssc_ctl_ovrd_in_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_cmn_sel[2]),
  .cr_self_clr (1'b0)
);

// ---------------------------------------------------------------------
// %%CREG MPLLA_SSC_EN_OVRD_IN - Override values for incoming MPLLA SSC enable
//   OFFSET: 0x03
//   ATTR: READ,WRITE
//   FIELDS:
//      [1] MPLLA_SSC_EN_OVRD_EN   - Override enable for MPLLA SSC enable
//          RESET: 0x0
//      [0] MPLLA_SSC_EN_OVRD_VAL  - Override value for MPLLA SSC enable
//          RESET: 0x0
//
// ---------------------------------------------------------------------
wire        mplla_ssc_en_ovrd_en_r;
wire        mplla_ssc_en_ovrd_val_r;
wire [15:0] mplla_ssc_en_ovrd_in_rd_data;

dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(2), .RST_VAL(2'b0_0), .MSK_VAL(2'd0))
 mplla_ssc_en_ovrd_in_reg (
  .cr_val      ({
                 mplla_ssc_en_ovrd_en_r,
                 mplla_ssc_en_ovrd_val_r
                }),
  .cr_rd_data  (mplla_ssc_en_ovrd_in_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_cmn_sel[3]),
  .cr_self_clr (1'b0)
);

// ---------------------------------------------------------------------
// %%CREG MPLLB_BW_OVRD_IN - Override values for incoming MPLLB bandwidth
//   OFFSET: 0x04
//   ATTR: READ,WRITE
//   FIELDS:
//    [11] MPLLB_BW_OVRD_EN  - Override enable for mpllb_bandwidth[10:0]
//         RESET: 0x0
//  [10:0] MPLLB_BW_OVRD_VAL - Override value for mpllb_bandwidth[10:0]
//         RESET: 0x43
//
// ---------------------------------------------------------------------
wire        mpllb_bandwidth_ovrd_en_r;
wire [10:0] mpllb_bandwidth_ovrd_val_r;
wire [15:0] mpllb_bw_ovrd_in_rd_data;

dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(12), .RST_VAL(12'b0_00001000011), .MSK_VAL(12'd0))
 mpllb_bw_ovrd_in_reg (
  .cr_val      ({
                 mpllb_bandwidth_ovrd_en_r,
                 mpllb_bandwidth_ovrd_val_r
                }),
  .cr_rd_data  (mpllb_bw_ovrd_in_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_cmn_sel[4]),
  .cr_self_clr (1'b0)
);

// ---------------------------------------------------------------------
// %%CREG MPLLB_SSC_CTL_OVRD_IN - Override values for incoming MPLLB SSC control settings
//   OFFSET: 0x05
//   ATTR: READ,WRITE
//   FIELDS:
//     [15] MPLLB_SSC_CTL_OVRD_EN  - Override value for MPLLB SSC control settings
//          RESET: 0x0
//  [14:12] MPLLB_SSC_CLK_SEL      - Override value for mpllb_ssc_clk_sel[2:0]
//          RESET: 0x5
//   [11:3] MPLLB_FRACN_CTRL       - Override value for mpllb_fracn_ctrl[8:0]
//          RESET: 0x0
//    [2:0] MPLLB_SSC_RANGE        - Override value for mpllb_ssc_range[2:0]
//          RESET: 0x0
//
// ---------------------------------------------------------------------
wire        mpllb_ssc_ctl_ovrd_en_r;
wire [2:0]  mpllb_ssc_clk_sel_r;
wire [8:0]  mpllb_fracn_ctrl_r;
wire [2:0]  mpllb_ssc_range_r;
wire [15:0] mpllb_ssc_ctl_ovrd_in_rd_data;

dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(16), .RST_VAL(16'b0_101_000000000_000), .MSK_VAL(16'd0))
 mpllb_ssc_ctl_ovrd_in_reg (
  .cr_val      ({
                 mpllb_ssc_ctl_ovrd_en_r,
                 mpllb_ssc_clk_sel_r,
                 mpllb_fracn_ctrl_r,
                 mpllb_ssc_range_r
                }),
  .cr_rd_data  (mpllb_ssc_ctl_ovrd_in_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_cmn_sel[5]),
  .cr_self_clr (1'b0)
);

// ---------------------------------------------------------------------
// %%CREG MPLLB_SSC_EN_OVRD_IN - Override values for incoming MPLLB SSC enable
//   OFFSET: 0x06
//   ATTR: READ,WRITE
//   FIELDS:
//      [1] MPLLB_SSC_EN_OVRD_EN   - Override enable for MPLLB SSC enable
//          RESET: 0x0
//      [0] MPLLB_SSC_EN_OVRD_VAL  - Override value for MPLLB SSC enable
//          RESET: 0x0
//
// ---------------------------------------------------------------------
wire        mpllb_ssc_en_ovrd_en_r;
wire        mpllb_ssc_en_ovrd_val_r;
wire [15:0] mpllb_ssc_en_ovrd_in_rd_data;

dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(2), .RST_VAL(2'b0_0), .MSK_VAL(2'd0))
 mpllb_ssc_en_ovrd_in_reg (
  .cr_val      ({
                 mpllb_ssc_en_ovrd_en_r,
                 mpllb_ssc_en_ovrd_val_r
                }),
  .cr_rd_data  (mpllb_ssc_en_ovrd_in_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_cmn_sel[6]),
  .cr_self_clr (1'b0)
);

// ---------------------------------------------------------------------
// %%CREG LANE_FSM_OP_XTND - Lane FSM OP XTND control register
//   OFFSET: 0x07
//   ATTR: READ,WRITE
//   FIELDS:
//      [0] LANE_FSM_OP_XTND - Required when accessing the analog CREGs in firmware to prevent timing violations across ANA-DIG interface.
//          RESET: 0x0
//
// ---------------------------------------------------------------------
wire [15:0] cr_lane_fsm_op_xtnd_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b0), .MSK_VAL(1'b0)) 
 lane_fsm_op_xtnd_reg (
  .cr_val      ({
                 lane_fsm_op_xtnd_r
                 }),
  .cr_rd_data  (cr_lane_fsm_op_xtnd_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_cmn_sel[7]),
  .cr_self_clr (1'b0)
);

// Muxed register read for RAW_PCS registers
//     
assign cr_cmn_rd_data =  cr_cmn_ctl_rd_data            |
                         mplla_bw_ovrd_in_rd_data      |
                         mplla_ssc_ctl_ovrd_in_rd_data |
                         mplla_ssc_en_ovrd_in_rd_data  |
                         mpllb_bw_ovrd_in_rd_data      |
                         mpllb_ssc_ctl_ovrd_in_rd_data |
                         mpllb_ssc_en_ovrd_in_rd_data  |
                         cr_lane_fsm_op_xtnd_rd_data   |
                         cr_cmn_aon_rd_data;

/////////////////////////
// Overriden ASIC Inputs
/////////////////////////

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(`DWC_E12MP_X4NS_MPLL_BW_WIDTH)) mplla_bandwidth_in (
  .asic           (mplla_bandwidth),
  .phy            (pma_mplla_bandwidth),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (`DWC_E12MP_X4NS_MPLL_BW_WIDTH'd67),
  .cr_ovrd        (mplla_bandwidth_ovrd_en_r),
  .cr_ovrd_val    (mplla_bandwidth_ovrd_val_r[`DWC_E12MP_X4NS_MPLL_BW_RANGE])
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(3)) mplla_ssc_range_in (
  .asic           (mplla_ssc_range),
  .phy            (pma_mplla_ssc_range),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (3'b111),
  .cr_ovrd        (mplla_ssc_ctl_ovrd_en_r),
  .cr_ovrd_val    (mplla_ssc_range_r)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(9)) mplla_fracn_ctrl_in (
  .asic           (mplla_fracn_ctrl),
  .phy            (pma_mplla_fracn_ctrl),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (9'b000000000),
  .cr_ovrd        (mplla_ssc_ctl_ovrd_en_r),
  .cr_ovrd_val    (mplla_fracn_ctrl_r)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(3)) mplla_ssc_clk_sel_in (
  .asic           (mplla_ssc_clk_sel),
  .phy            (pma_mplla_ssc_clk_sel),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (3'b101),
  .cr_ovrd        (mplla_ssc_ctl_ovrd_en_r),
  .cr_ovrd_val    (mplla_ssc_clk_sel_r)
);

dwc_e12mp_phy_x4_ns_asic_in mplla_ssc_en_in (
  .asic           (mplla_ssc_en),
  .phy            (pma_mplla_ssc_en),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b1),
  .cr_ovrd        (mplla_ssc_en_ovrd_en_r),
  .cr_ovrd_val    (mplla_ssc_en_ovrd_val_r)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(`DWC_E12MP_X4NS_MPLL_BW_WIDTH)) mpllb_bandwidth_in (
  .asic           (mpllb_bandwidth),
  .phy            (pma_mpllb_bandwidth),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (`DWC_E12MP_X4NS_MPLL_BW_WIDTH'd67),
  .cr_ovrd        (mpllb_bandwidth_ovrd_en_r),
  .cr_ovrd_val    (mpllb_bandwidth_ovrd_val_r[`DWC_E12MP_X4NS_MPLL_BW_RANGE])
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(3)) mpllb_ssc_range_in (
  .asic           (mpllb_ssc_range),
  .phy            (pma_mpllb_ssc_range),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (3'b111),
  .cr_ovrd        (mpllb_ssc_ctl_ovrd_en_r),
  .cr_ovrd_val    (mpllb_ssc_range_r)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(9)) mpllb_fracn_ctrl_in (
  .asic           (mpllb_fracn_ctrl),
  .phy            (pma_mpllb_fracn_ctrl),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (9'b000000000),
  .cr_ovrd        (mpllb_ssc_ctl_ovrd_en_r),
  .cr_ovrd_val    (mpllb_fracn_ctrl_r)
);

dwc_e12mp_phy_x4_ns_asic_in #(.WIDTH(3)) mpllb_ssc_clk_sel_in (
  .asic           (mpllb_ssc_clk_sel),
  .phy            (pma_mpllb_ssc_clk_sel),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (3'b101),
  .cr_ovrd        (mpllb_ssc_ctl_ovrd_en_r),
  .cr_ovrd_val    (mpllb_ssc_clk_sel_r)
);

dwc_e12mp_phy_x4_ns_asic_in mpllb_ssc_en_in (
  .asic           (mpllb_ssc_en),
  .phy            (pma_mpllb_ssc_en),
  .clk            (1'b0),
  .rst            (1'b0),
  .test_ovrd      (1'b0),
  .test_ovrd_val  (1'b1),
  .cr_ovrd        (mpllb_ssc_en_ovrd_en_r),
  .cr_ovrd_val    (mpllb_ssc_en_ovrd_val_r)
);

// Synchronize mplla_force_en to cr_clk domain
dwc_e12mp_phy_x4_ns_gen_sync sync_mplla_force_en (
  .q   (mplla_force_en_sync),
  .clk (cr_clk),
  .rst (cr_rst),
  .d   (mplla_force_en)
);

// Synchronize mpllb_force_en to cr_clk domain
dwc_e12mp_phy_x4_ns_gen_sync sync_mpllb_force_en (
  .q   (mpllb_force_en_sync),
  .clk (cr_clk),
  .rst (cr_rst),
  .d   (mpllb_force_en)
);

// Synchronize rtune_req to cr_clk domain
dwc_e12mp_phy_x4_ns_gen_sync sync_rtune_req (
  .q   (rtune_req_sync),
  .clk (cr_clk),
  .rst (cr_rst),
  .d   (rtune_req)
);

// OR with force_en and send un-flopped version to the Raw PCS lanes
// (Mantis 5662)
assign cmn_mplla_en_out = (lane_mplla_en_in | mplla_force_en_sync);
assign cmn_mpllb_en_out = (lane_mpllb_en_in | mpllb_force_en_sync);

// Common outputs to PMA
// (flop combination logic before sending to PMA, bec async)
always @(posedge cr_clk or posedge cr_rst) begin
  if (cr_rst) begin
    mplla_en <= 1'b0;
    mpllb_en <= 1'b0;
    pma_rtune_req <= 1'b0;
  end
  else begin
    mplla_en <= cmn_mplla_en_out;
    mpllb_en <= cmn_mpllb_en_out;
    // Mantis 6264
    // Need to aggregate rtune request from lanes
    pma_rtune_req <= lane_rtune_req_in | rtune_req_sync;
  end
end 

endmodule
